{"data":{"jobs":{"edges":[{"node":{"frontmatter":{"title":"SoC RTL Design Engineer","company":"5G Testbed R&D Lab IITH","location":"Hyderabad, India","range":"Dec 2023 - Present","url":""},"html":"\n- Designed and owned the Noise Covariance block for ULPI-powered 32TR Massive MIMO radio unit, targeting high performance and area-efficient timing goals.
\n- Knowledge on integrating high-speed Ethernet I/O interface IP, handling multi-clock domain designs with rigorous CDC debugging in simulation and hardware.
\n- Contributed to micro-architecture and development of an Ethernet debug architecture, enabling a 25G SFP link for O-RAN Massive MIMO ULPI IP.
\n- Debugged and optimized modem core IPs for the 5G NR UE PHY Baseband subsystem, specifically focusing on the Synchronization Signal Block (SSB) Receiver chain.
\n- Collaborated with cross-functional teams across architecture, validation, and software to enable seamless HW-SW co-design and integrated new features into the SoC.
\n- Improved productivity by exploring and implementing new automation tools to execute test plans and analyze results effectively.
\n
"}},{"node":{"frontmatter":{"title":"Research Project Trainee","company":"5G Testbed R&D Lab IITH","location":"Hyderabad, India","range":"Dec 2022 - Nov 2023","url":""},"html":"\n- Assisted in developing fundamental DSP modules with fixed-point implementation in HDL, focusing on synthesis optimization and code linting.
\n- Integrated Soft interface IPs such as DDR4 controllers and DMA to support required system functionality for 5G NR Systems.
\n- Automated EDA tool flows by developing Make, Tcl, and Python scripts, significantly reducing manual effort.
\n- Performed unit testing with Cocotb to ensure hardware reliability and functional correctness of RTL modules.
\n- Managed build and automated testing environments by integrating Jenkins with Docker container agents.
\n
"}},{"node":{"frontmatter":{"title":"Future Wireless Communications Intern","company":"IIT Hyderabad","location":"Hyderabad, India","range":"Aug 2022 - Nov 2022","url":""},"html":"\n- Gained foundational knowledge in digital design and communication systems by building basic modules with Vivado, Vitis, and MATLAB.
\n- Designed and implemented basic DSP modules using High-Level Synthesis (HLS) for rapid prototyping of wireless communication blocks.
\n- Developed digital logic for embedded systems using PlatformIO, Arduino, and IDF frameworks across Verilog, Assembly, and Avr-gcc.
\n- Configured FPGA and ARM cores on the Vaman board using Termux for mobile-based hardware interaction and debugging.
\n- Applied Matrix Analysis and optimization techniques (including cvxpy, gradient ascent, and descent) in Python to solve signal processing problems.
\n
"}}]}}}