{"data":{"featured":{"edges":[{"node":{"frontmatter":{"title":"Memory Tester System","cover":{"childImageSharp":{"gatsbyImageData":{"layout":"constrained","placeholder":{"fallback":"data:image/jpeg;base64,/9j/2wBDABALDA4MChAODQ4SERATGCgaGBYWGDEjJR0oOjM9PDkzODdASFxOQERXRTc4UG1RV19iZ2hnPk1xeXBkeFxlZ2P/2wBDARESEhgVGC8aGi9jQjhCY2NjY2NjY2NjY2NjY2NjY2NjY2NjY2NjY2NjY2NjY2NjY2NjY2NjY2NjY2NjY2NjY2P/wgARCAAPABQDASIAAhEBAxEB/8QAGAAAAgMAAAAAAAAAAAAAAAAAAAUDBAb/xAAWAQEBAQAAAAAAAAAAAAAAAAACAAH/2gAMAwEAAhADEAAAAYGVFqjmwNv/xAAZEAACAwEAAAAAAAAAAAAAAAABAgADBBH/2gAIAQEAAQUCzoruc1XJkIFhYcn/xAAUEQEAAAAAAAAAAAAAAAAAAAAQ/9oACAEDAQE/AT//xAAUEQEAAAAAAAAAAAAAAAAAAAAQ/9oACAECAQE/AT//xAAeEAABAwQDAAAAAAAAAAAAAAABABAREiEiMUFRkf/aAAgBAQAGPwI1ahGx9Yz0jlw3/8QAGxAAAwACAwAAAAAAAAAAAAAAAAEREDEhQVH/2gAIAQEAAT8hWmitijlaYPZobz24h0f/2gAMAwEAAgADAAAAEEwv/8QAFREBAQAAAAAAAAAAAAAAAAAAEBH/2gAIAQMBAT8Qp//EABURAQEAAAAAAAAAAAAAAAAAAAEQ/9oACAECAQE/EEn/xAAbEAEBAAMAAwAAAAAAAAAAAAABEQAhMUFxwf/aAAgBAQABPxAH1XpEaH3J8Bpt2YcMZWFAhfJlSoShhd75hx6z/9k="},"images":{"fallback":{"src":"/static/12f9506cea4275af9f549c1d56244bb9/2f91a/project_1.jpg","srcSet":"/static/12f9506cea4275af9f549c1d56244bb9/7face/project_1.jpg 175w,\n/static/12f9506cea4275af9f549c1d56244bb9/4e6eb/project_1.jpg 350w,\n/static/12f9506cea4275af9f549c1d56244bb9/2f91a/project_1.jpg 700w","sizes":"(min-width: 700px) 700px, 100vw"},"sources":[{"srcSet":"/static/12f9506cea4275af9f549c1d56244bb9/0bd01/project_1.avif 175w,\n/static/12f9506cea4275af9f549c1d56244bb9/322d8/project_1.avif 350w,\n/static/12f9506cea4275af9f549c1d56244bb9/67d5a/project_1.avif 700w","type":"image/avif","sizes":"(min-width: 700px) 700px, 100vw"},{"srcSet":"/static/12f9506cea4275af9f549c1d56244bb9/ac411/project_1.webp 175w,\n/static/12f9506cea4275af9f549c1d56244bb9/15c18/project_1.webp 350w,\n/static/12f9506cea4275af9f549c1d56244bb9/cc91e/project_1.webp 700w","type":"image/webp","sizes":"(min-width: 700px) 700px, 100vw"}]},"width":700,"height":519}}},"tech":["Verilog / System Verilog","SoC","DDR","AXI","Platform Designer","Quartus Prime Pro"],"github":"https://github.com/velicharlagokulkumar/quartus/tree/main/G3","external":"","cta":null},"html":"<p>The Memory Tester System is controlled by an ARM processor, generating Custom test patterns and writing them to a specified location in DDR4 SDRAM.</p>"}}]}}}